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A transaction ends with a STOP condition, which is defined as
SDA transitioning from 0 to 1 with SCL HIGH, as shown in
Figure 21.
During a read from the FAN5702 (Figure 24), the master
issues a “Repeated Start” after sending the register address
and before resending the slave address. The “Repeated Start”
Slave Releases
Master Drives
t HD;STO
is a 1-to-0 transition on SDA while SCL is HIGH, as shown in
Figure 22.
SDA
ACK(0) or
NACK(1)
SDA
Slave Releases
ACK(0) or
NACK(1)
t SU;STA
t HD;STA
SLADDR
MS Bit
SCL
SCL
Figure 21. Stop Bit
Figure 22 Repeated Start Timing
Read and Write Transactions
The following figures outline the sequences for data read and write. Bus control is signified by the shading of the packet, defined
as
Master Drives Bus
and
Slave Drives Bus
. All addresses and data are MSB first.
Table 5. I C bit Definitions for Figure 23 and Figure 24.
2
Symbol
S
A
A
R
P
Definition
START. See Figure 20.
ACK. The slave drives SDA to 0 to acknowledge the preceding packet.
NACK. The slave sends a 1 to NACK the preceding packet.
Repeated START. See Figure 22.
STOP. See Figure 21.
7 bits
0
8 bits
0
8 bits
0
S
Slave Address
0
A
Reg Addr
A
Data
A
P
Figure 23. Write Transaction
7 bits
0
8 bits
0
7 bits
0
8 bits
1
S
Slave Address
0
A
Reg Addr
A
R
Slave Address
1
A
Data
A
P
Figure 24. Read Transaction
? 2010 Fairchild Semiconductor Corporation
FAN5702 ? Rev. 1.0.4
14
www.fairchildsemi.com
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